1. Field
This disclosure relates generally to semiconductor integrated circuits, and more specifically, to electrostatic discharge protection for semiconductor integrated circuits.
2. Related Art
Electrostatic discharge (ESD) protection continues to be very significant for integrated circuits (ICs). Typically, all or nearly all of the I/O cells for an IC require ESD protection. But this ESD protection occupies area in each of these cells, and therefore adds to IC die size and cost. This problem is particularly acute for high pin count ICs. Clearly, meeting IC ESD protection targets while minimizing ESD area is an important design goal.
An I/O library typically includes various functional I/O cells, as well as other elements such as power cells, ground cells, spacer cells and corner cells. These cells are typically mixed as needed for the functional IC and abutted to form a continuous “pad ring” around the perimeter of the IC die. Considering the south side of an IC, the abutted I/O library cells form a horizontal I/O bank. The cells in this bank each typically contain wide metal power and ground buses in one or more metal layers which serve, when the cells are horizontally abutted, to provide continuous power and ground buses across the extent of the bank. The power and ground buses connect to bond pads, typically in power and ground cells of the I/O library. In an IC with a wire-bond package, these pads connect via bond wires to power and ground pins in the package.
ESD clamps are typically placed in the pad ring and electrically connected between the power and ground rails as part of an ESD protection scheme. Since these clamps can be quite large, they are often placed in the power or ground cells. Unfortunately, since even wide metal power and ground buses have non-zero resistance and typical ESD events can produce very high currents, IR drops in the buses can be a serious problem. The efficacy of an ESD clamp in a power or ground cell for protecting an ESD stressed I/O pad reduces with increasing spacing in the I/O bank between the I/O cell containing the stressed I/O pad and the power or ground cells containing ESD clamps. One option to address the problem of IR drops in the power buses is to require more frequent placement of power and ground cells in the pad ring. But this approach can be expensive in terms of overall pad ring area. An alternate solution is to distribute smaller ESD clamps in all the I/O cells of the bank. These distributed ESD clamp networks, where multiple small clamps in vicinity of any ESD stressed I/O pad work in parallel to absorb an ESD event, can be very efficient. Considering that each I/O cell will have an incremental power and ground bus resistance across its physical width, the distributed ESD clamp network can be thought of as a resistive ladder network of incremental power and ground bus resistances with ESD clamp elements connected between the buses after each resistance increment. Therefore for any I/O cell receiving ESD stress from an I/O pad to local ground, the ESD current density will be highest in the clamp local to the stressed I/O cell, and decrease in each clamp element moving further away, in both directions, from the stressed I/O cell. In contrast to clamps placed infrequently in power/ground cells, with the distributed clamp approach, a smaller total clamp area is required and every I/O cell may exhibit comparable ESD robustness.
It is well known in the industry that average IC pin counts have increased steadily over the years. Consider an I/O library, with a given cell width, and an IC with a given size of the IC core circuitry which the perimeter pad-ring should enclose. With increasing pin count, a point is reached where the area inside the required pad ring exceeds the area of the core circuitry. These “pad-limited” designs are wasteful in terms of IC area. One alternative is to add a second pad ring around the die periphery. These dual I/O cell row designs are typically built with the same I/O library elements used in single row designs. In the physical design of a typical dual I/O cell row IC, the inner and outer I/O cell banks are configured independently, with a gap between the two banks. ESD clamp elements, either large clamps in power/ground cells, or smaller clamps in distributed networks in all the I/O cells, are placed in both rows, generally following the same clamp placement rules as defined for single row designs. Considering again the south edge of an IC, the power and ground buses in both the inner and outer I/O cell banks connect by the usual horizontal abutment. Vertical power and ground bus connections between the horizontal buses in the inner and outer I/O cell rows, if desired, can be implemented with special vertical “jumper cells.” But in order to provide low-resistance connections sufficient for routing ESD currents, these jumper cells need to be very wide (on the order of an I/O cell width) to include adequate bus metal width. Since these jumper cells horizontally displace other I/O library cells in both banks when placed in the dual row pad ring, their use is typically minimized to save overall area.